1. Field of the Invention
This invention relates to a system for communication between semiconductor chips on a semiconductor substrate.
2. Brief Description of the Prior Art
Optical I/O or optical interconnects are a powerful method to solve the I/O bottlenecks of high speed computing and signal processing (P. R. Haugen et al. "Optical Interconnects For High Speed Computing", Optical Engineering Vol. 25., pp. 1076, Oct. 1986). The technology required to implement optical I/O, however is not yet in place. First, most optical fiber technology is based upon 1.3 to 1.5 micrometer wavelength which was developed to handle one-on-one long distance communication. It is extremely difficult to adapt optical fiber technology for wafer level multiple access I/O systems The effort to develop dedicated optical I/O chip through opto electronic inteqrated circuit (OEIC) technology (T. Iwama et al. "4.times.4 OEIC Switch Modules Using GaAs Substrate", IEEE Journal of Lightwave Technology, Vol 6, pp. 772, Jun. 1988) also found limited success because of the difficulty to integrate GaAs based OEIC chips with silicon VLSI chips in a hybrid manner.
Prior art complex semiconductor circuits have often been constructed by use of plastic or ceramic circuit boards having semiconductor packages mounted thereon with interconnection or communication between semiconductor packages taking place via conductors formed on the circuit board. Problems of heat dissipation and cross talk are minimized in such circuits by spreading out the components sufficiently on the circuit board surface. It is also known in the prior art that, as the signal being communicated increases to a clock rate of over about 50 megahertz, the conductors on the printed circuit board begin to act as transmission lines and display capacitive and inductive properties. It is therefore necessary that appropriate measures be taken as in the case of transmission lines to obtain proper impedance matching to avoid reflections and the like. This problem is relatively minor and, in general, no particular attention was needed in the past if the check rate was below about 10 megahertz. However, with the continued emphasis in high speed operation of the components and with the increased miniaturization of the integrated circuit chips themselves and the desire for higher packing density on the printed circuit boards, the above noted problems become more and more of a bottleneck. For example, the number of pins entering and exiting integrated circuit packages has remained relatively constant since the package size and chip size have remained relatively constant. However, the number of components contained on the chip has continually increased. According to Ruth's law, the number of pins out of the chip is proportional to K.sup.2/3, where K is the number of gates on the chip. It follows that the number of pins on the package cannot increase whereas the necessity to do so exists. The problem of insufficient pins has been remedied in the prior art by multiplexing. However, multiplexing defeats the desire for high speed operation. Also, there is an increase in the problem of matching each pin and the path thereto or therefrom from reflections and other transmission line type problems. Furthermore, substantial heat will be generated in the input and output drivers, both from the increase in component packing density per chip as well as the increase in packing density of the chips on the printed circuit board.